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Publications (Link)

    GPU triggered networking for intra-kernel communications, Michael LeBeane, Khaled Hamidouche, Brad Benton, Mauricio Breternitz, Steven K Reinhardt, Lizy K John, International Conference for High Performance Computing, Networking, Storage and Analysis, 2017

    Extended Task Queueing: Active Messages for Heterogeneus Systems, M.Lebeane et al, Supercomputing, 2016
    PY-PITS: A scalable Python Runtime System for the computation of Partially Idempotents Tasks , E.Borin et al MPP 2016 Workshop on Parallel Programming Models (best paper award)
    HadoopCL2: Motivating the Design of a Distributed, Heterogeneous Programming System With Machine-Learning Applications M. Grossman, M. Breternitz, V. Sarkar. IEEE Transactions on Parallel and Distributed Systems, issue 99, 2015
    Optimizing Big Data Analytics on Heterogeneous Processors, Tutorial, IEEE Conference Big Data 2015, M. Daga, J.
    Gu, M. Breternitz Adaptive global power optimization for Web servers. Piga, Leonardo, Mauricio Breternitz et al. The Journal of Supercomputing (2014): 1-25.
    Implementation and evaluation of deep neural networks (DNN) on mainstream heterogeneous systems Junli Gu, Mauricio Breternitz et al. Proceedings of 5th Asia-Pacific Workshop on Systems. ACM, 2014.
    HadoopCL: MapReduce on Distributed Heterogeneous Platforms Through Seamless Integration of Hadoop and OpenCL.M. Grossman, M. Breternitz, V. Sarkar. "" 2013 International Workshop on High Performance Data Intensive Computing. May 2013.
    Characterizing APU Performance in HadoopCL on Heterogeneous Distributed Platforms, M. Grossman, M. Breternitz, V. Sarkar, AMD Developer Summit 2013.
    Cloud Workload Analysis with SWAT, M.Breternitz, K.Lowery, A.Chernoff, P.Kaminski, L.Piga, SBAC-PAD 2012 - International Conference on Computer Architecture, New York, NY
    Efficient Image Re-Ranking Computation on GPUs, D.Pedronette, R.Torres, Ed.Borin, M.Breternitz ISPA 2012
    LAR-CC: Large Atomic regions with conditional Commits, Borin, E; Wu, Y; Breternitz, M; Wang, CGO'2011- IEEE/ACM 9th Annual International Symposium on Code Generation and Optimization, Apr 2-6, 2011
    Structure-Constrained Microcode Compression, Borin,E; Araujo, G; Breternitz, M; Wu, Y SBAC-PAD 2011 - 23rd International Symposium on Computer Architecture and High-Performance Computing, Oct /2011
    Face Detection: Performance opportunities for CPU-GPU Kernel Migration in Fusion Architecture, Breternitz, M; Chernoff, A; Kaminski; P; Lowery, K., AMD Fusion Developer Summit, June 11-14/2011
    TAO - Two Level Atomicity for Dynamic Binary Optimizations, E.Borin, Y.Wu, C.Wang, W.Liu, M.Breternitz, S.Hu, E.Natanzon, S.Rotem, R.Rosner. CGO'2011- IEEE/ACM 8th Annual International Symposium on Code Generation and Optimization
    Segmented Bloom Filter Algorithm for Efficient Predictors, M. Breternitz, G.H.Loh, B.Black, J.Rupley, P.Sassone, W.Attrot, Y.Wu, SBAC-PAD Conference, 2008
    StarDBT: An Efficient Multi-platform Dynamic Binary Translation System, C.Wang, S.Hu, H-S Kim,S.Nair, M.Breternitz, Z.Ying, Y.Wu, APAC Conference, 2007
    Clustering-Based Microcode Compression, Edson Borin, Mauricio Breternitz Jr, Youfeng Wu, Guido Araujo, ICCD-2006 Enhanced Code Density of Embedded CISC Processors with Echo Technology, Youfeng Wu, Mauricio Breternitz, Herbert Hum, Ramesh Peri, and Jay Pickett, CODES+ISSS 2005
    Echo Technology for Memory Constrained Processors, Youfeng Wu, Mauricio Breternitz Jr., Herbert Hum, Ramesh Peri, Jay Pickett, CTCES 2004
    The Accuracy of Initial Prediction in Two-Phase Dynamic Binary Translators, Youfeng Wu, Mauricio Breternitz Jr., Justin Quek, Orna Etzion, Jesse Fang; International Symposium on Code Generation and Optimization with Special Emphasis on Feedback-Directed and Runtime Optimization CGO 2004; Page(s): 227-238.
    Continuous Trip Count Profiling for Loop Optimizations in Two-Phase Dynamic Binary Translators; Youfeng Wu, Mauricio Breternitz Jr., Tevi Devor; INTERACT-8 Interaction between Compilers and Computer Architectures, 2004; Page(s): 3-12.
    Compilation, Architectural Support, and Evaluation of SIMD Graphics Pipeline Programs on a General-Purpose CPU.; Mauricio Breternitz Jr., Herbert H. J. Hum, Sanjeev Kumar; Proceedings 12th International Conference on Parallel Architectures and Compilation Techniques - PACT 2003; Page(s): 135-145.
    Enhanced Compression Techniques to Simplify Programm Decompression and Execution.; Mauricio Breternitz Jr., Roger Smith; ICCD 1997; Page(s): 170-176. The Motorola PowerPC PEEK profiler; Stewart, K.; Butt, F.; Sarkisian, D.; Breternitz, M., Jr.; Performance, Computing, and Communications Conference, 1997. IPCCC 1997., IEEE International , 1997; Page(s): 342-349.
    Design tradeoffs and experience with Motorola PowerPC migration tools; Breternitz, M.; Manikonda, A.; Ommerman, M.; Su, W.; Thornton, A.; Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on , 1996; Page(s): 301-308.
    Motorola PowerPC Migration Tools-emulation and translation; Afzal, T.; Breternitz, M.; Kacher, M.; Menyhert, S.; Ommerman, M.; Su, W.; Compcon '96. 'Technologies for the Information Superhighway' Digest of Papers , 1996; Page(s): 145-150.
    Solutions and debugging for data consistency in multiprocessors with noncoherent caches.; Bernstein, D.; Breternitz, M., Jr.; Gheith, A.M.; Mendelson, B.; International Journal of Parallel Programming, vol.23, no.1, Feb. 1995.; Page(s) 83103.
    An optimal asynchronous scheduling algorithm for software cache consistency; Simons, B.; Sarkar, V.; Breternitz, M., Jr.; Lai, M.; System Sciences, 1994. Vol.II: Software Technology, Proceedings of the Twenty-Seventh Hawaii International Conference on , 1994; Page(s): 502-511.
    Implementation Optimization Techniques for Architecture Synthesis of Application-Specific Processors.; Mauricio Breternitz Jr., John Paul Shen; MICRO-24 1991; Page(s): 114-123.
    Adapting AIX to a shared memory cluster.; Breternitz, M., Jr.; Gheith, A.; Jindal, A.; Lehr, T.; Proceedings. SHARE Europe Anniversary Meeting. Client/Server - the Promise and the Reality. Carouge/Geneva, Switzerland: SHARE Europe, 1993.; Page(s): 415-428.
    Architecture synthesis of high-performance application-specific processors; Breternitz, M., Jr.; Shen, J.P.; Design Automation Conference, 1990. 27th ACM/IEEE , 1990; Pg(s): 542-548.
    Tradeoffs between pipelining and multiple functional units in fine grain parallelism exploitation.; M. Breternitz and A. Nicolau. ICS-90 International Conference on Supercomputing, Santa Clara CA, April 1989.
    Organization Of Array Data For Concurrent Memory Access; Breternitz, M.; Shen, J.P.; Microprogramming and Microarchitecture, 1988., Proceeding of the 21st Annual Workshop on; 97-99.
    The White Dwarf: a high-performance application-specific processor; Wolfe, A.; Breternitz, M., Jr.; Stephens, C.; Ting, A.L.; Kirk, D.B.; Bianchini, R.P., Jr.; Shen, J.P.;, 1988.15th Annual International Symposium on Computer Architecture, 1988; Page(s): 212-222.